1. Field of the Invention
This invention relates to data processing systems and more particularly to logic for allowing a plurality of processors to share a plurality of memories primarily used by the processors.
2. Description of the Related Art
In the prior art, memory access arrangements are taught but they all have shortcomings. In one arrangement, a single memory is dedicated to and accessed by a single processor. While this speeds read/write access time by the processor to its dedicated memory, the efficiency of use of the memory is low. For systems having more than one processor, other memories must also be provided, and each processor is limited to accessing only its own memory. This requires much memory and is expensive.
Another approach is to have one common memory connected to a bus and the memory is accessed by two or more processors. While less memory needs to be provided, and efficiency of use of the common memory increases, very often more than one processor wants to access the common memory at the same time. This causes one or more of the processors to wait which decreases their efficiency of use. To overcome this problem cache memories are provided for each processor, as is known in the art, but this increases both circuit complexity and cost.
Accordingly, there is a need in the art for a multiple processor, multiple shared memory arrangement wherein each of the processors can access any one of the memories without preventing another processor from accessing another of the memories at the same time.